The purpose of the role is to develop and maintain products (units, nodes, networks, systems and solutions). Includes all development activities (requirement analysis, system design, architecture design, hardware design, software design, integration, verification, simulations, tools design, PLM support, product documentation).

Tasks:

• Collect verification requirements and document verification plans

• Analyze and improve the UVM testbench architecture

• Develop verification environments for new features

• Verify the IP towards FPGA and ASIC targets

• Contribute in planning backlog and Scrum sprint planning

• Coach, support and possibly lead other verifiers in the team

• Interface towards other Subsystem, ASIC and FPGA teams

• Perform trouble shooting and customer support

• Drive continuous improvements of products, development environment and processes

• Develop competence in technical domain

Required competence:

The following is needed to be successful in this role:

• At least 5 years’ experience in ASIC or FPGA verification and simulation on IP, sub-system and/or chip level using SystemVerilog UVM

• Experience in defining and implementing UVM test environments including coverage closure

• Good competence in VHDL and/or System Verilog

• Some experience in Scripting, System-C or C / C++ experience

• Experience in continuously improved and optimizing ways of working

• Fluent in English, speaking and writing

• A Bachelor’s or Master degree in Computer/Electrical Engineering (or equivalent)