Role

The three major 5G services, eMBB, uRLLC, and mMTC, pose great challenges to baseband processing. The computing power needs to be improved by 100 times, the latency is shortened from 10 ms to 0.05 ms, and the energy efficiency is improved by 50 times. Baseband computing evolves from "decades" to "hundreds" and is entering the "thousand-core era". Baseband processor is evolving from vector to wide vector processing and is evolving to ultra-wide vector and even tensor. The baseband computing architecture also evolves from heterogeneous acceleration to Baseband Domain Specific Architecture. We need experts with extensive experience in computer architecture to help achieve this challenge.

Responsibility

1. Design the heterogeneous parallel system and explore the future 5G/6G heterogeneous parallel system framework to achieve extremely energy efficiency, flexible combination, and extremely low latency.

2. To meet future requirements for low latency and flexibility in multiple scenarios, make breakthroughs in key technologies of the baseband system based on the evolution trend of the SOC and Core microarchitectures, and take responsibility for the competitiveness of the baseband system.

Requirements

Qualifications and experience

1. Target Students. students who graduated in 2020/2021 and For excellent PhDs, it can be extended to 2019

2. Have an in-depth understanding of cutting-edge heterogeneous computing and be familiar with hardware architecture principles such as CPU, GPU, and ARM. Experience in HPC development, optimization, and algorithm design is preferred.

3. Have knowledge in embedded SW, and hands-on skills in block design with Verilog/VHDL. C++ or SystemC experience is strongly required.

4. Knowledge of RTL design and verification processes, time sequence closure, ASIC/FPGA/CGRA integrated technologies is preferred.

5. Have strong team communication and collaboration capabilities, self-driven, and technical enthusiasm.